Substrate for device bonding, device bonded substrate, and method for producing same

ABSTRACT

A substrate for device bonding includes a substrate having an electrode layer and a solder layer formed on the electrode layer, wherein the solder layer is a Pb-free solder layer which comprises (1) a base metal composed of (i) Sn, (ii) Sn and Au, or (iii) In, (2) at least one metal selected from the group consisting of Bi, In (only in the case where the base metal is Sn, or Sn and Au), Zn, Au (only in the case where the base metal is In) and Sb, and (3) at least one metal selected from the group consisting of Ag, Ni, Fe, Al, Cu and Pt, and the solder layer has a thickness of 1 to 15 μm and a surface roughness (Ra) of not more than 0.11 μm.

TECHNICAL FIELD

The present invention relates to a substrate for device bonding which isused for bonding or fixing devices, a device bonded substrate in which adevice has been bonded to the substrate for device bonding, and aprocess for producing the substrate for device bonding.

BACKGROUND ART

With the spread of cellular phones and optical communications, ceramicsubstrates have been employed as substrates for mounting semiconductordevices of high output and high power consumption which work in thehigh-frequency region, such as GaAs type FET, Si—Ge type HBT, Si typeMOSFET and GaN type laser diode, for the reason of low dielectric lossat high frequencies. Of the ceramic substrates, aluminum nitridesintered substrates are particularly paid attention because they haveexcellent characteristics that the thermal conductivity is high and thecoefficient of thermal expansion is close to that of semiconductordevices.

For bonding a device onto a ceramic substrate such as an aluminumnitride sintered product, it is general that a first and a secondundercoating metal layers firmly bonded to the ceramic substrate areformed by metallization, then on the undercoating metal layer anelectrode layer composed of a noble metal such as gold is formed, andthe device is soldered to the electrode layer. For soldering the device,a reflow process is frequently adopted from the viewpoint of efficiency.Therefore, a solder layer of a specific pattern for bonding the deviceneeds to be previously formed on the electrode layer of the substrate.

As the semiconductor devices are integrated more highly in recent years,the solder layer needs to be formed in an extremely small area on thesubstrate for the reflow process with higher precision using thinfilm-forming technique. The solder layer is generally formed bylaminating various metal thin film layers successively in such a mannerthat a prescribed solder composition should be obtained when the solderlayer is molten. Such a solder layer is referred to as a “thinfilm-laminated solder layer” hereinafter, and a ceramic substrate havingan electrode layer on which the thin film-laminated solder layer hasbeen formed is referred to as a “ceramic substrate with a thinfilm-laminated solder layer” hereinafter.

As such a ceramic substrate with a thin film-laminated solder layer,there is known a substrate having an Au—Sn type thin film-laminatedsolder layer (see patent document 1), a substrate having a thinfilm-laminated solder layer that gives a Sn-37 wt % Pb eutectic solderhaving a melting point of 183° C. or gives a solder containing thiseutectic solder and a small amount of a different metal (these soldersbeing also referred to as “Sn—Pb eutectic solders” genericallyhereinafter) in the melting stage (see patent document 2), or the like.The Sn—Pb eutectic solders are most popular as electronically industrialsolders and have widely spread, and they can bond devices with high bondstrength even in case of a thin film-laminated solder layer (e.g.,solder layer shown in FIG. 12 in which a Pb layer and a Sn layer arelaminated alternately).

On the other hand, so-called Pb-free solders containing no leadcomponent have been employed recently because harmfulness of lead hasbecome a problem. As the Pb-free solders, those having a melting pointequivalent to that of the Sn—Pb eutectic solvers are desired from theviewpoint of substitutes for the Sn—Pb eutectic solders, and as suchPb-free solders, a Sn—Zn—In type solder (see patent document 3) and aSu—Ag—Bi type solder (see patent document 4) are known. These solders,however, are alloy solders previously prepared so as to have aprescribed composition, and any example of the thin film-laminatedsolder layer using such Pb-free solders is not known. In the presentspecification, the solder layer composed of an alloy solder previouslyprepared so as to have a prescribed composition is called an “alloysolder layer” for convenience and distinguished from the aforesaid thinfilm-laminated solder layer.

Pertinent background art includes the following Japanese patentdocuments:

Patent document 1: Japanese Patent Laid-Open Publication No.373960/2002;

Patent document 2: Japanese Patent Laid-Open Publication No.186884/1993;

Patent document 3: Japanese Patent Laid-Open Publication No.155984/1995; and

Patent document 4: Japanese Patent Laid-Open Publication No.200288/2003.

In the case of a ceramic substrate with a thin film-laminated solderlayer, Pb-freeing is an important technical problem, and it has beenheretofore been desired to convert a thin film-laminated solder layerthat gives a Sn—Pb solder in the melting stage into a Pb-free thinfilm-laminated solder layer.

In the case of the thin film-laminated solder layer, however, the wholelayer gives a prescribed solder composition when the layers are molten,so that its performance is greatly influenced by the layer structuredifferently from an alloy solder layer (this is apparent also from thelater-described comparison between the examples and the comparativeexamples). For example, even if high bond strength is obtained by thealloy solder layer, sufficient bond strength is not obtained frequentlyby the thin film-laminated solder layer that is formed so as to give thesame composition as that of the alloy solder layer in the melting stage.Further, the process to bond a device to a ceramic substrate having aSn—Pb eutectic thin film-laminated solder layer has been established,and therefore, in the shift to the Pb-free thin film-laminated solderlayer from the Sn—Pb eutectic thin film-laminated solder layer, it isrequired that bond strength equivalent to that obtained by the Sn—Pbeutectic thin film-laminated solder layer should be obtained, andbesides there is no large modification of the process. In order tosatisfy these requirements, the Pb-free thin film-laminated solder layeradopted needs to have a melting point of 170 to 230° C. preferably 180to 200° C.

It is an object of the present invention to provide a substrate fordevice bonding which has a Pb-free thin film-laminated solder layersatisfying the above requirements.

SUMMARY OF THE INVENTION

In order to solve the above problem, the present inventors have havefound that by the addition of metals such as Bi and In to a Pb-freesolder such as a Sn type solder containing Au, the resulting solder canhave a melting point almost equivalent to that of a Sn—Pb eutecticsolder. However, it has been also found that there is a problem of lowbond strength in the case where a device is soldered by the use of suchthin film-laminated solder layer incorporated with the above metals. Inorder to solve this problem, the present inventors have further foundthat high bond strength is sometimes obtained by adding specific metalssuch as Ag, bond strength is strongly influenced by the surfaceroughness of the thin film-laminated solder layer surface, and when thesurface roughness is lower than a specific value, high bond strength isobtained. Furthermore, the present inventors have succeeded in finding amethod for stably forming a solder layer having a surface roughnesssatisfying this condition. Based on the finding, the present inventionhas been accomplished.

That is to say, the subject matter of the present invention is asfollows.

[1] A substrate for device bonding, comprising a substrate having anelectrode layer and a solder layer formed on the electrode layer,wherein the solder layer is a Pb-free solder layer comprising:

(1) a base metal comprising (i) Sn, (ii) Sn and Au, or (iii) In,

(2) at least one metal selected from the group consisting of Bi, In(only in the case where the base metal is Sn, or Sn and Au), Zn, Au(only in the case where the base metal is In) and Sb, and

(3) at least one metal selected from the group consisting of Ag, Ni, Fe,Al, Cu and Pt,

and

the solder layer has a thickness of 1 to 15 μm and a surface roughness(Ra) of not more than 0.11 μm.

[2] The substrate for device bonding as stated in [1], wherein thesolder layer comprises:

(1) a base metal layer comprising (i) Sn, (ii) Sn and Au, or (iii) In,

(2) one or more melting point-lowering metal layers each of whichcomprises at least one metal selected from the group consisting of Bi,In (only in the case where the base metal is Sn, or Sn and Au), Zn, Au(only in the case where the base metal is In) and Sb, and

(3) one or more surface-smoothing metal layers each of which comprisesat least one metal selected from the group consisting of Ag, Ni, Fe, Al,Cu and Pt,

and

each of the melting point-lowering metal layers is adjacent to any oneof the surface-smoothing metal layers.

[3] A process for producing the substrate for device bonding as statedin [1] or [2], comprising a solder layer-forming step for forming aPb-free solder layer on an electrode layer of a substrate having anelectrode layer, said Pb-free solder layer comprising:

(1) a base metal comprising (i) Sn, (ii) Sn and Au, or (iii) In,

(2) at least one metal selected from the group consisting of Bi, In(only in the case where the base metal is Sn, or Sn and Au), Zn, Au(only in the case where the base metal is In) and Sb, and

(3) at least one metal selected from the group consisting of Ag, Ni, Fe,Al, Cu and Pt,

said Pb-free solder layer having a thickness of 1 to 15 μm and a surfaceroughness (Ra) of not more than 0.11 μm,

wherein the solder layer-forming step includes one or more steps forforming a layer comprising the base metal, one or more steps for forminga melting point-lowering metal layer comprising at least one metalselected from the group consisting of Bi, In (only in the case where thebase metal is Sn, or Sn and Au), Zn, Au (only in the case where the basemetal is In) and Sb, and one or more steps for forming asurface-smoothing metal layer comprising at least one metal selectedfrom the group consisting of Ag, Ni, Fe, Al, Cu and Pt, and

immediately before and/or immediately after the step for forming themelting point-lowering metal layer, any one of the steps for forming thesurface-smoothing metal layer is carried out.

[4] A process for producing the substrate for device bonding as statedin [1] or [2], comprising a bonding layer-forming step for forming abonding layer comprising a transition metal on an electrode layer of asubstrate having an electrode layer and a solder layer-forming step forforming a Pb-free solder layer on the bonding layer, said Pb-free solderlayer comprising:

(1) a base metal comprising (i) Sn, (ii) Sn and Au, or (iii) In,

(2) at least one metal selected from the group consisting of Bi, In(only in the case where the base metal is Sn, or Sn and Au), Zn, Au(only in the case where the base metal is In) and Sb, and

(3) at least one metal selected from the group consisting of Ag, Ni, Fe,Al, Cu and Pt,

said Pb-free solder layer having a thickness of 1 to 15 μm and a surfaceroughness (Ra) of not more than 0.11 μm,

wherein the solder layer-forming step includes one or more steps forforming a layer comprising the base metal, one or more steps for forminga melting point-lowering metal layer comprising at least one metalselected from the group consisting of Bi, In (only in the case where thebase metal is Sn, or Sn and Au), Zn, Au (only in the case where the basemetal is In) and Sb, and one or more steps for forming asurface-smoothing metal layer comprising at least one metal selectedfrom the group consisting of Ag, Ni, Fe, Al, Cu and Pt, and

immediately before and/or immediately after the step for forming themelting point-lowering metal layer, any one of the steps for forming thesurface-smoothing metal layer is carried out.

[5] A process for producing a device bonded substrate, comprisingplacing a device having an electrode on the solder layer of thesubstrate for device bonding as stated in [1] or [2] in such a mannerthat the electrode of the device is brought into contact with the solderlayer and then bonding the device by reflow soldering.

[6] A device bonded substrate produced by the process as stated in [5].

According to the substrate for device bonding of the invention, itbecomes possible to bond semiconductor devices without using a Sn—Pbeutectic solder that is considered to have a fear of harmfulness.Further, since the solder used in the substrate for device bonding ofthe invention has a melting point of almost the same level as that of aSn—Pb eutectic solder, a conventional reflow process using a Sn—Pbeutectic solder can be adopted without largely modifying the process,and it becomes possible to solder semiconductor devices with high bondstrength at low temperatures. In particular, a ceramic substrate whichcontains aluminum nitride as a main component on which an electrodelayer has been formed is very excellent substrate for device bonding,which has, in addition to the above merits, both of a merit of lowdielectric loss at high frequencies and a merit of excellent heatdischarging properties to dissipate heat that is generated when thedevice is used.

According to the production process of the invention, it is possible toefficiently produce the above-mentioned excellent substrate for devicebonding.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a sectional view of a substrate for device bonding of thepresent invention used in Example 1;

FIG. 2 is a sectional view of a substrate for device bonding of thepresent invention used in Example 2;

FIG. 3 is a sectional view of a substrate for device bonding of thepresent invention used in Example 3;

FIG. 4 is a sectional view of a substrate for device bonding of thepresent invention used in Example 4;

FIG. 5 is a sectional view of a substrate for device bonding of thepresent invention used in Example 5;

FIG. 6 is a sectional view of a substrate for device bonding of thepresent invention used in Example 6;

FIG. 7 is a sectional view of a substrate for device bonding of thepresent invention used in Example 7;

FIG. 8 is a sectional view of a substrate for device bonding of thepresent invention used in Example 8;

FIG. 9 is a sectional view of a substrate for device bonding used inComparative Example 1;

FIG. 10 is a sectional view of a substrate for device bonding used inComparative Example 2;

FIG. 11 is a sectional view of a substrate for device bonding used inComparative Example 3;

FIG. 12 is a sectional view of a conventional substrate for devicebonding with a Sn—Pb solder used in Reference Example 1;

FIG. 13 is a photograph of a polished section of a substrate for devicebonding used in Example 1;

FIG. 14 is a photograph of a polished section of a substrate for devicebonding used in Example 2;

FIG. 15 is a photograph of a polished section of a substrate for devicebonding used in Example 3;

FIG. 16 is a photograph of a polished section of a substrate for devicebonding used in Comparative Example 1;

FIG. 17 is a three-dimensional image obtained by measuring a solderlayer surface of a substrate for device bonding used in Example 1 bymeans of AFM;

FIG. 18 is a three-dimensional image obtained by measuring a solderlayer surface of a substrate for device bonding used in Example 2 bymeans of AFM;

FIG. 19 is a three-dimensional image obtained by measuring a solderlayer surface of a substrate for device bonding used in Example 3 bymeans of AFM; and

FIG. 20 is a three-dimensional image obtained by measuring a solderlayer surface of a substrate for device bonding used in ComparativeExample 1 by means of AFM.

DETAILED DESCRIPTION OF THE INVENTION

The substrate for device bonding of the invention comprises a substratehaving an electrode layer and a solder layer formed on the electrodelayer, wherein the solder layer is a Pb-free solder layer comprising (1)a base metal composed of (i) Sn, (ii) Sn and Au, or (iii) In, (2) atleast one metal selected from the group consisting of Bi, In (only inthe case where the base metal is Sn, or Sn and Au), Zn, Au (only in thecase where the base metal is In) and Sb, and (3) at least one metalselected from the group consisting of Ag, Ni, Fe, Al, Cu and Pt, and thesolder layer has a thickness of 1 to 15 μm and a surface roughness (Ra)of not more than 0.11 μm.

The “substrate having an electrode layer” in the invention is notspecifically restricted so long as being a substrate on a part or all ofa surface of which an electrode layer composed of a noble metalfunctioning as an electrode has been formed, but from the viewpoint thatdielectric loss at high frequencies is low when a semiconductor devicebonded to the substrate is used, it is preferable to use a metallizedsubstrate obtained by forming a noble metal layer on a ceramic substratesuch as aluminum nitride, alumina or SiC, or a Si substrate,particularly a ceramic substrate having a surface roughness Ra of notmore than 0.05 μm and Rmax of not more than 0.2 μm, by means ofmetallization. Although Au, Ag, Pd, Pt or the like is employable as thenoble metal to constitute the electrode layer, Au having extremely lowconduction resistance is preferably employed.

In the metallized substrate, the noble metal electrode layer isgenerally formed directly or indirectly on an undercoating metal layerthat is firmly bonded to the ceramic substrate, as previously described.In case of, for example, an alumina substrate, there can be preferablyemployed a metallized substrate obtained by printing an electrodepattern composed of a paste of a high-melting point metal such astungsten or molybdenum on an alumina green sheet, sintering the patternand the green sheet simultaneously, then forming a nickel layer on thehigh-melting point metal layer if necessary, and further forming thereona noble metal layer such as a gold layer. In case of a ceramic substratecontaining aluminum nitride as a main component, there can beparticularly preferably employed a metallized substrate obtained by (i)a process comprising adding a sintering agent to an aluminum nitridepowder, molding the mixture to thereby sintering the same, then forminga metal layer (first undercoating layer) containing titanium as a maincomponent and having basically the same shape as that of the electrodepattern on a surface of the sintered substrate by sputtering or the likeand then forming, as an electrode layer, a layer containing platinum asa main component on the first undercoating layer by sputtering or thelike similarly to the above, or a metallized substrate obtained by (ii)a process comprising further forming an electrode layer of gold or thelike on the platinum layer as the second undercoating layer bysputtering or the like. In the substrate for device bonding of theinvention, it is particularly preferable to use the aluminum nitridetype metallized substrate obtained by the above process (i) or (ii) fromthe viewpoint that heat discharging properties to dissipate heat that isgenerated when a device bonded thereto is used are excellent.

In the present invention, the thickness of the solder layer is in therange of 1 to 15 μm, and from the viewpoints of precision bonding of adevice and bond strength, the thickness is in the range of preferably 2to 8 μm. If the thickness of the solder layer is less than 1 μm,sufficient bond strength is not obtained occasionally. If the thicknessthereof exceeds 15 μm, a trouble that a side surface or an upper surface(light emission surface in case of semiconductor device) of the deviceis obscured by the solder after bonding sometimes takes place becausethe amount of the solder is too large.

In the present invention, the surface roughness (Ra) of the solder layeris not more than 0.11 μm, preferably not more than 0.06 μm, particularlypreferably not more than 0.05 μm. When the surface roughness (Ra) of thesolder layer is in this range, high bond strength is obtained when adevice is soldered. If the surface roughness exceeds 0.11 μm, high bondstrength is not obtained in some cases. The bond strength is sensitivealso to the surface profile of the solder layer, and therefore, inaddition to the Ra of the above range, Rmax is preferably not more than0.90 μm, more preferably not more than 0.55 μm.

The term “surface roughness (Ra)” used herein is an arithmetic meanvalue of surface protrusions and depressions based on the center planeof the measuring region, and is one parameter obtained by numericallyexpressing shapes and sizes of protrusions and depressions of thesurface. The term “Rmax” is a difference in height between the highestpoint and the lowest point of the surface.

In the present invention, measurements of the surface roughness (Ra) andthe Rmax are carried out using AFM (atomic force microscope). The AFMcan three-dimensionally measure fine surface profile of a sample byresolution of atomic level (A order), and by image processing of theresulting three-dimensional profile, accurate surface roughness (Ra) andRmax can be determined.

The base metal is an essential component of a solder, and is a componentto primarily determine the melting point of the solder and to make basicbond strength appear. As the base metal, (i) Sn, (ii) Sn and Au, or(iii) In is employable, and for the reason of high reliability afterbonding, it is preferable to use (i) Sn or (ii) Sn and Au.

The content of the base metal in the solder layer is in the range ofpreferably 10 to 95% by weight, particularly preferably 34 to 90% byweight, based on the total weight of the solder layer. In the case where(ii) Sn and Au are used as the base metals, it is preferable that thecontent of Sn is in the range of 80 to 99% by weight and the content ofAu is in the range of 1 to 20% by weight, based on the total weight ofthe base metals, and from the viewpoint of bond strength, it is mostpreferable that the content of Sn is in the range of 87 to 97% by weightand the content of Au is in the range of 3 to 13% by weight, based onthe total weight of the base metals.

The melting point-lowering metal has a function of lowering a meltingpoint of the solder layer. The melting point-lowering metal is at leastone metal selected from the group consisting of Bi, In, Zn, Au and Sb.However, use of In as the melting point-lowering metal is restricted tothe case where the base metal is Sn, or Sn and Au, and use of Au as themelting point-lowering metal is restricted to the case where the basemetal is In. For the reason that the melting point lowering effect onall the base metals is high, Bi is preferably used as the meltingpoint-lowering metal. In the case where the base metal is Sn, or Sn andAu, In can also be preferably used as well as Bi, for the same reason.The In has not only a melting point lowering effect but also has anadvantage that cushioning effect at the bonding is high because Initself is soft.

The content of the melting point-lowering metal is in the range ofpreferably 0.1 to 30% by weight, particularly preferably 3 to 16% byweight, based on the total weight of the solder layer, from theviewpoints of a melting point and bond strength of the solder layer.When the content of the melting point-lowering metal is in this range,the melting point of the solder layer can be made to be in the range of170 to 230° C., preferably 180 to 200° C. If the content of the meltingpoint-lowering metal is low, the melting point of the solder layer tendsto be raised. If the content thereof is less than the lower limit of theabove range, the melting point of the solder layer frequently exceeds230° C.

The surface-smoothing metal has a function of smoothing a surface of thesolder layer. It is preferable to use Ag as the surface smoothing metalbecause Ag has a high surface smoothing effect and also has a meltingpoint lowering effect.

The content of the surface-smoothing metal is in the range of preferably4.9 to 60% by weight, particularly preferably 7 to 50% by weight, basedon the total weight of the solder layer, from the viewpoint of thesurface smoothing effect.

In the solder layer, components, such as Ga, Pd, P, Mn, Cr, Ti and rareearth elements, may be contained when needed, with the proviso that thecontent of these components is less than 20% by weight, preferably lessthan 10% by weight, based on the total weight of the solder layer.

In case of the substrate for device bonding of the invention having asolder layer of the above properties, it is possible to carry outsoldering of device with high bond strength in the temperature range of170 to 230° C., and a conventional reflow process for Sn—Pb eutecticsolders can be adopted without modifying the process largely.

In the present invention, the existence form of the various componentscontained in the solder layer is not specifically restricted. That is tosay, the solder layer may be, for example, the aforesaid thinfilm-laminated solder layer or an alloy solder layer, but because a finepattern can be formed with high precision, the solder layer ispreferably the thin film-laminated solder layer. There is no specificlimitation on the method for forming the thin film-laminated solderlayer, and for example, sputtering, ion plating, deposition, CVD methodand plating are preferable.

In the case where the solder layer in the invention is a thinfilm-laminated solder layer, it is preferable that the solder layercomprises (1) a base metal layer composed of (i) Sn, (ii) Sn and Au, or(iii) In, (2) one or more melting point-lowering metal layers each ofwhich is composed of at least one metal selected from the groupconsisting of Bi, In (only in the case where the base metal is Sn, or Snand Au), Zn, Au (only in the case where the base metal is In) and Sb,and (3) one or more surface-smoothing metal layers each of which iscomposed of at least one metal selected from the group consisting of Ag,Ni, Fe, Al, Cu and Pt, and each of the melting point-lowering metallayers is adjacent to any one of the surface-smoothing metal layers.When the base metal layer is composed of Sn and Au, the base metal layermay have such a single layer structure of homogeneous composition as isformed by depositing Sn and Au simultaneously, or may have a multi-layerstructure including one or more Sn layers and one or more Au layers.Further, the aforesaid arbitrary components, such as Ga, Pd, P, Mn, Cr,Ti and rare earth elements, can be introduced at the formation of thebase metal layer.

As the layer structure wherein the melting point-lowering metal layer isadjacent to the surface-smoothing metal layer, there can be mentionedthree kinds of layer structures, i.e., a layer structure wherein thesurface-smoothing metal layer is present on the melting point-loweringmetal layer, a layer structure wherein the surface-smoothing metal layeris present under the melting point-lowering metal layer, and a layerstructure wherein the surface-smoothing metal layers are present on andunder the melting point-lowering metal layer.

In case of the layer structure wherein the surface-smoothing metal layeris present on the melting point-lowering metal layer, the meltingpoint-lowering metal layer is formed on a layer (e.g., layer of Pb-freesolder) other than the surface-smoothing metal layer at the formation ofthe thin film-laminated solder layer. In this case, the meltingpoint-lowering metal is partially aggregated, so that the resultingmelting point-lowering metal layer is not a smooth continuous layer andhas a rough surface. However, when a surface-smoothing metal layer isfurther formed thereon, the rough surface is restored presumably by theinteraction between the melting point-lowering metal and thesurface-smoothing metal, whereby a smooth surface is provided.

In case of the layer structure wherein the surface-smoothing metal layeris present under the melting point-lowering metal layer, the meltingpoint-lowering metal layer is formed on the surface-smoothing metallayer at the formation of the thin film-laminated solder layer. Theresulting melting point-lowering metal layer is a smooth continuouslayer though aggregation slightly occurs.

In case of the layer structure wherein the surface-smoothing metallayers are present on and under the melting point-lowering metal layer,aggregation of the melting point-lowering metal most hardly occurs atthe formation of the thin film-laminated solder layer, and the resultingmelting point-lowering metal layer is a continuous layer of highsmoothness.

As described above, if the melting point-lowering metal layer isadjacent to the surface-smoothing metal layer in the solder layer, themelting point-lowering metal layer becomes a continuous layer of smoothsurface, and even if the melting point-lowering metal is temporarilyaggregated to form a discontinuous layer, this layer is restored by thesurface-smoothing metal layer laminated thereon and has a smoothsurface. Therefore, the solder layer finally obtained has high surfacesmoothness and exhibits great bonding power when a device is bonded. Ofthe above layer structures, the layer structure wherein thesurface-smoothing metal layer is present on and under the meltingpoint-lowering metal layer is particularly preferable because a solderlayer having highest smoothness and greatest bonding ability isobtained.

On the other hand, in the case where the melting point-lowering metallayer is not adjacent to any surface-smoothing metal layer, the meltingpoint-lowering metal layer is aggregated at the formation of the thinfilm-laminated solder layer and is not restored, so that the finallyobtained solder layer has low surface smoothness, and when a device isbonded, sufficient bonding ability is not obtained in some cases. As aresult, soldering in the temperature range of 170 to 230° C. with highbond strength sometimes becomes feasible.

In the substrate for device bonding of the invention, between theelectrode layer and the solder layer, a layer composed of a noble metal(e.g., Pt) other than the noble metal for forming the electrode layerand a bonding layer (e.g., Ti layer) may be present in this order fromthe electrode layer side.

Next, preferred embodiments of the solder layers having the aforesaidspecific layer structures are described in detail referring to theattached drawings.

For example, such a layer structure as is shown in FIG. 1 wherein asurface-smoothing metal layer 500, a gold-tin alloy (also referred to as“Au10—Sn”) layer 501 having a gold content of 10% by weight as a basemetal layer, a melting point-lowering metal layer 502 such as a Bilayer, a surface-smoothing metal layer 503 and an Au10—Sn layer 504 arelaminated in this order; such a layer structure as is shown in FIG. 2wherein a surface-smoothing metal layer 500, a melting point-loweringmetal layer 511, a surface-smoothing metal layer 512 and an Au10—Snlayer 513 are laminated in this order; and such a layer structure as isshown in FIG. 3 wherein a surface-smoothing metal layer 500, a meltingpoint-lowering metal layer 521 and an Au10—Sn layer 522 are laminated inthis order are preferable.

In the above embodiments, the thickness of each layer is properlydetermined taking the whole composition into consideration. In theembodiment shown in FIG. 1, the thickness of the Au10—Sn layer 501located at the nearer side to the substrate is preferably 1/32 to ½ ofthe thickness of the Au10—Sn layer 504 located at the farther side fromthe substrate.

The thickness of the surface-smoothing metal layer 500 present as thelowest layer in the solder layer is in the range of preferably 0.1 to 5μm, particularly preferably 0.2 to 3 μm, from the viewpoint of costperformance. If the thickness of this layer is less than 0.1 μm, thesurface smoothing effect is low. Even if the thickness is more than 5μm, the surface smoothing effect is almost the same as that of a layerhaving a thickness of 0.2 to 3 μm. This surface-smoothing metal layer ispreferably composed of Ag.

There is no specific limitation on the process for producing thesubstrate for device bonding of the invention. For example, thesubstrate for device bonding can be obtained by forming a solder layerof the aforesaid composition on an electrode layer of a substrate havingan electrode layer and then polishing the surface of the solder layer sothat the thickness and the surface roughness of the solder layer shouldsatisfy the aforesaid requirements. However, for the reason that thesubstrate for device bonding can be simply and readily obtained in highyields with high reproducibility, it is preferable to adopt thefollowing process (process of the invention). That is to say, it ispreferable to adopt a process for producing a substrate for devicebonding, comprising a solder layer-forming step for forming a Pb-freesolder layer on an electrode layer of a substrate having an electrodelayer, said Pb-free solder layer comprising (1) a base metal composed of(i) Sn, (ii) Sn and Au, or (iii) In, (2) at least one metal selectedfrom the group consisting of Bi, In (only in the case where the basemetal is Sn, or Sn and Au), Zn, Au (only in the case where the basemetal is In) and Sb, and (3) at least one metal selected from the groupconsisting of Ag, Ni, Fe, Al, Cu and Pt, and said Pb-free solder layerhaving a thickness of 1 to 15 μm and a surface roughness (Ra) of notmore than 0.11 μm, wherein the solder layer-forming step includes one ormore steps for forming a layer composed of the base metal, one or moresteps for forming a melting point-lowering metal layer composed of atleast one metal selected from the group consisting of Bi, In (only inthe case where the base metal is Sn, or Sn and Au), Zn, Au (only in thecase where the base metal is In) and Sb, and one or more steps forforming a surface-smoothing metal layer composed of at least one metalselected from the group consisting of Ag, Ni, Fe, Al, Cu and Pt, andimmediately before and/or immediately after the step for forming themelting point-lowering metal layer, any one of the steps for forming thesurface-smoothing metal layer is carried out.

In the above production process, the solder layer does not necessarilyhave to be formed directly on the electrode layer of the substratehaving an electrode layer, and it is possible that a bonding layercomposed of a transition metal is formed on the electrode layer of thesubstrate having an electrode layer and then the solder layer is formedon the bonding layer.

There is no specific limitation on the method to bond a device such as asemiconductor device to the substrate for device bonding of theinvention, and soldering methods publicly known are adoptable withoutany restriction. For the reason that bonding of high precision can beefficiently carried out, it is preferable that a device having anelectrode is placed on the solder layer of the substrate for devicebonding of the invention in such a manner that the electrode of thedevice is brought into contact with the solder layer and then the deviceis bonded by reflow soldering. The reflow soldering is a processcomprising supplying a solder to a prescribed land of a substrate or anelectrode of a part or both of them, fixing the part at a given positionof the substrate, and then melting the solder (allowing the solder toflow) to bond the part and the substrate to each other. In this process,a method for allowing the solder to reflow is not specificallyrestricted, and a method using a reflow conveyer, a method using a hotplate, vapor reflowing, etc. are adoptable. The heating temperature andthe heating time are properly determined according to the type of thesolder used. In the case where the substrate for device bonding of theinvention is used, excellent soldering can be carried out at almost thesame temperature as that for bonding a device to a ceramic substratehaving a solder pattern of a Sn—Pb eutectic thin film-laminatedstructure, specifically 170 to 230° C., preferably 180 to 200° C.

As the “device” to be bonded by soldering, a device having an electrodecomposed of a metal capable of being bonded with a solder is employed.Examples of such devices include electrical parts, such as resistors andcapacitors, and semiconductor devices having electrodes capable of beingdirectly connected to other electrical wirings. In the devices generallyused in the semiconductor field, the electrodes are usually composed ofgold, but the electrode employable in the invention is not limitedthereto.

In the case where the lowest layer in the solder layer is asurface-smoothing metal layer, if the solder layer is heated and moltenby the above-mentioned device bonding method, the surface-smoothingmetal diffuses into the whole of the molten solder layer. In this case,all of the surface-smoothing metal that constitutes thesurface-smoothing metal layer does not necessarily diffuse, and thesurface-smoothing metal sometimes remains in the form of a layer in thevicinity of the bottom surface of the surfaced-smoothing metal layer.

EXAMPLES

The present invention is further described with reference to thefollowing examples, but it should be construed that the invention is inno way limited to those examples.

Example 1

A substrate for device bonding having such a structure as is shown inFIG. 1 was prepared in the following manner. FIG. 1 is a sectional viewof a typical substrate for device bonding 101 of the present invention.The substrate 200 consists of an aluminum nitride sintered substrate201, a first undercoating layer 202 containing Ti as a main component, asecond undercoating layer 203 containing platinum as a main componentand a gold electrode layer 204 laminated in this order. The substratefor device bonding 101 has a structure wherein on a gold electrode layer204 of the substrate 200, a solder flow-out preventing Pt layer 301, abonding layer 401 containing Ti as a main component and a solder layer509 are laminated, wherein the solder layer 509 consists of a first Aglayer 500, a first Au10—Sn layer 501, a Bi layer 502, a second Ag layer503 and a second Au10—Sn layer 504 laminated in this order.

First, on a surface of an aluminum nitride sintered substrate (50.8mm×50.8 mm×0.3 mm (thickness), surface roughness (Ra): 0.02 μm, Rmax:0.179 μm, available from Tokuyama Corporation), the first undercoatinglayer containing Ti as a main component and having a thickness of 0.06μm, the second undercoating layer containing platinum as a maincomponent and having a thickness of 0.2 μm, and a gold electrode layerhaving a thickness of 0.6 μm were laminated in this order by the use ofa sputtering apparatus. Subsequently, patterning for preventing flow-outof solder was performed by photolithography, and the Pt layer having athickness of 0.25 μm was formed by sputtering. Then, solder patterningwas performed by photolithography, and on the solder flow-out preventingPt, the Ti bonding layer having a thickness of 0.06 μm and the Ag layerhaving a thickness of 1.5 μm were formed by the use of a vacuumdeposition apparatus. Subsequently, the Au—Sn layer composed of an Au—Snalloy (melting point: 217° C., Young's modulus: 45.0 GPa (at 25° C.))having a gold content of 10% by weight and having a thickness of 1.0 μmwas formed by two-element simultaneous deposition using Au and Sn astargets, then the Bi layer having a thickness of 0.33 μm and the Aglayer having a thickness of 0.2 μm were formed, and finally the Au—Snlayer having a gold content of 10% by weight and having a thickness of2.47 μm was formed by two-element simultaneous deposition using Au andSn. Thus, a substrate for device bonding (No. 1) of the invention wasprepared.

The substrate for device bonding thus obtained was measured on thesurface roughness, and as a result, Ra was 0.058 μm and Rmax was 0.689μm. The measurement of surface roughness was carried out in thefollowing manner using Digital Instruments Contact AFM NanoScope III.That is to say, a double-sided tape was stuck to the opposite side tothe solder layer surface side of the substrate for device bonding of theinvention, and the substrate for device bonding was fixed to a steelcircular plate having a diameter of 12 mm. Then, the circular plate wasfixed on an upper part of a piezo-scanner by a magnetic method, and acantilever equipped with a probe was brought into contact with thesolder layer surface. The cantilever responds to protrusions ordepressions of the solder layer surface directly and is displaced. Thedisplacement was measured by an “optical lever method”. The cantileverused was a V-shaped cantilever made of Si₃N₄, having a spring constantof 0.12 N/m, a probe height of 3 μm, a curvature radius of 5 to 40 nmand a ½ cone angle of 35° and having a tip shape of quadrangularpyramid. Prior to the measurement, static elimination using a staticelimination blower was carried out to reduce influences by staticelectricity of the substrate surface to the lowest. The measuring rangewas a range of 20 μm square, and the number of measuring fields of viewwas 3 per 1 chip of the substrate for device bonding. After themeasurement, image processing of the measured three-dimensional profilewas carried out using a softwear of NanoScope III to calculate Ra andRmax, and a mean value of the 3 fields of view was determined. In thepresent invention, Ra is a mean value on a surface based on the centerplane of the measuring range and is calculated from the formula (1).Rmax is a difference in height between the highest point and the lowestpoint of the surface.Ra=F(1, L _(X) L _(Y))I(0, L _(Y) ,I(0, L _(X) |f(x,y)|dx)dy)  (1)wherein f(x,y) represents a surface based on the center plane, and L_(X)and L_(Y) represent dimensions of the surface.

Subsequently, on the solder layer of the substrate for device bondingprepared as above, a Ga—As semiconductor device having an Au electrodewas placed, and the semiconductor device was bonded at 220° C. for 180seconds by the use of a die bonder to prepare a device bonded substrate.Similarly, 10 device bonded substrates were prepared, and their bondstrength was measured by a die shear tester (manufactured by IMADAInc.). As a result, the mean bond strength was 3.1 kgf/mm², and themodes of peeling were all “inside semiconductor device”. The meltingpoint of the solder layer in the examples and the comparative exampleswas determined by DTA measurement using a Seiko Instruments TG/DTAapparatus SSC-5200.

Further, substrates for device bonding No. 2 to No. 8 of the inventionwere prepared by changing each thickness of the Bi layer, the Au—Snlayer having a gold content of 10% by weight (Au10—Sn layer) and the Aglayer as shown in Table 1, and then measurements of surface roughnessand bond strength were carried out in the same manner as above. Theresults are set forth in Table 1.

The expression that the mode of peeling is “inside semiconductor device”means that peeling is caused by breakage of a semiconductor device, andthe expression that the mode of peeling is “inside solder layer” meansthat peeling is caused by breakage of a solder layer. Breakage of asemiconductor device takes place at 2.5 kgf/mm² or more. It is generallysaid that when the mode of peeling is “inside solder layer”, the meanbond strength is desired to be 2.0 kgf/mm² or more from the viewpoint ofreliability. Further, it can be said that when peeling takes placebetween a semiconductor device and a solder, bond reliability is low. Inthe composition of a solder layer in Table 1, a component other than Au,Bi and Ag is Sn, so that the amount (% by weight) of Sn is omitted.

TABLE 1 Thickness of Thickness of first Ag layer Thickness Thickness ofBi second Ag Thickness Composition of (surface- of first layer (meltinglayer (surface- of second solder layer soomthing Au10-Sn point-loweringsoomthing Au10—Sn (balance is Sn) metal layer) layer metal layer) metallayer) layer Au Bi Ag No. (μm) (μm) (μm) (μm) (μm) (wt %) (wt %) (wt %)Example 1 1 1.5 1 0.33 0.2 2.47 5.61 6.71 37.13 2 1.5 1 0.164 0.2 2.6365.92 3.36 37.39 3 1.5 1 0.501 0.2 2.299 5.30 10.13 36.87 4 1.5 1 0.6750.2 2.125 4.98 13.55 36.60 5 1.5 0.077 0.33 0.2 2.393 5.61 6.71 37.13 61.5 1.235 0.33 0.2 1.235 5.61 6.71 37.13 7 1.5 1 0.348 0.81 1.842 4.446.85 48.73 8 0.2 1 0.33 0.2 2.47 7.39 9.38 12.20 Example 2 9 1.5 3.470.33 0.2 — 5.61 6.71 37.13 10 1.5 3.636 0.164 0.2 — 5.92 3.36 37.39 111.5 3.299 0.501 0.2 — 5.30 10.13 36.87 12 1.5 3.125 0.675 0.2 — 4.9813.55 36.60 13 1.5 3.13 0.34 0.4 — 5.11 6.99 41.89 14 1.5 2.842 0.3480.81 — 4.44 6.85 48.73 15 0.2 3.47 0.33 0.2 — 7.39 9.38 12.20 Example 316 1.5 3.67 0.33 — — 6.00 6.80 33.14 17 1.5 3.836 0.164 — — 6.32 3.4033.37 18 1.5 3.508 0.492 — — 5.70 10.06 32.91 19 1.5 3.336 0.664 — —5.38 13.48 32.68 Comp. 1.5 1.735 0.33 0.2 1.735 5.61 6.71 37.13 Ex. 1(No. 20) Mean bond Melting point strength of solder (kgf/mm²) Mainpeeling Ra Rmax No. layer (° C.) (n = 10) mode* (μm) (μm) Example 1 1180 3.1 inside SC D 0.058 0.689 2 186 2.9 inside SC D 0.055 0.659 3 1752.7 inside SC D 0.053 0.743 4 168 3.3 inside SC D 0.058 0.721 5 180 2.8inside SC D 0.056 0.681 6 180 2.2 inside SL 0.057 0.711 7 182 2.1 insideSL 0.061 0.744 8 181 3.2 inside SC D 0.052 0.672 Example 2 9 180 3.1inside SC D 0.044 0.390 10 186 2.8 inside SC D 0.047 0.516 11 175 2.9inside SC D 0.041 0.418 12 168 3 inside SC D 0.039 0.466 13 179 3.7inside SC D 0.048 0.432 14 185 2.3 inside SL 0.033 0.364 15 179 3.4inside SC D 0.044 0.452 Example 3 16 185 3.2 inside SC D 0.101 0.807 17193 2.8 inside SC D 0.106 0.898 18 182 3 inside SC D 0.104 0.902 19 1762.9 inside SC D 0.107 0.986 Comp. 185 0.7 between 0.120 1.060 Ex. 1SCD/SL (No. 20) *inside SC D = inside semiconductor device inside SL =inside solder layer between SCD/SL = between semiconductor device andsolder layer

Example 2

A substrate for device bonding was prepared in the same manner as inExample 1, except that the structure of the solder layer 510 was changedto that wherein on the first Ag layer 500 having a thickness of 1.5 μm,a Bi layer 511 having a thickness of 0.33 μm, a second Ag layer 512having a thickness of 0.2 μm and a first Au10—Sn layer 513 having athickness of 3.47 μm were laminated in this order, as shown in FIG. 2.Using the substrate for device bonding, a device bonded substrate (No.9) was prepared at the same bonding temperature as in Example 1.Similarly, 10 device bonded substrates were prepared, and the surfaceroughness and the bond strength of the device bonded substrates weremeasured in the same manner as in Example 1. As a result, Ra was 0.044μm, Rmax was 0.390 μm, the mean bond strength was 3.1 kgf/mm², and themodes of peeling were mainly “inside semiconductor device”. Further,substrates for device bonding No. 10 to No. 15 of the invention wereprepared by changing each thickness of the Bi layer, the Au10—Sn layerand the Ag layer as shown in Table 1, and then measurement of bondstrength was carried out in the same manner as above. The results areset forth in Table 1.

Example 3

A device bonded substrate (No. 16) was prepared in the same manner as inExample 1, except that the structure of the solder layer 520 was changedto that wherein on the first Ag layer 500 having a thickness of 1.5 μm,a Bi layer 521 having a thickness of 0.33 μm and a first Au10—Sn layer522 having a thickness of 3.67 μm were laminated in this order, as shownin FIG. 3. Similarly, 10 device bonded substrates were prepared, and thesurface roughness and the bond strength of the device bonded substrateswere measured in the same manner as in Example 1. As a result, Ra was0.101 μm, Rmax was 0.807 μm, the mean bond strength was 3.2 kgf/mm², andthe modes of peeling were mainly “inside semiconductor device”. Further,substrates for device bonding No. 17 to No. 19 of the invention wereprepared by changing each thickness of the Bi layer and the Au10—Snlayer as shown in Table 1, and then measurement of bond strength wascarried out in the same manner as above. The results are set forth inTable 1.

Example 4

A substrate for device bonding was prepared in the same manner as inExample 1, except that the structure of the solder layer 530 was changedto that wherein on the first Ag layer 500 having a thickness of 1.5 μm,a first Au10—Sn layer 531 having a thickness of 1.0 μm, an In layer 532having a thickness of 0.33 μm, a second Ag layer 533 having a thicknessof 0.2 μm and a second Au10—Sn layer 534 having a thickness of 2.47 μmwere laminated in this order, as shown in FIG. 4. Using the substratefor device bonding, a device bonded substrate (No. 21) was prepared atthe same bonding temperature as in Example 1. Similarly, 10 devicebonded substrates were prepared, and the surface roughness and the bondstrength of the device bonded substrates were measured in the samemanner as in Example 1. As a result, Ra was 0.049 μm, Rmax was 0.644 μm,the mean bond strength was 2.5 kgf/mm², and the modes of peeling weremainly “inside semiconductor device”. Further, substrates for devicebonding No. 22 to No. 28 of the invention were prepared by changing eachthickness of the In layer, the Au10—Sn layer and the second Ag layer asshown in Table 2, and then measurement of bond strength was carried outin the same manner as above. The results are set forth in Table 2.

TABLE 2 Thickness of Thickness of first Ag layer Thickness Thickness ofIn second Ag Thickness Composition of (surface- of first layer (meltinglayer (surface- of second solder layer soomthing Au10-Sn point-loweringsoomthing Au10—Sn (balance in Sn) metal layer) layer metal layer) metallayer) layer Au In Ag No. (μm) (μm) (μm) (μm) (μm) (wt %) (wt %) (wt %)Example 4 21 1.5 1 0.33 0.2 2.47 5.71 5.06 37.79 22 1.5 1 0.164 0.22.636 5.97 2.51 37.72 23 1.5 1 0.501 0.2 2.299 5.44 7.70 37.86 24 1.5 10.675 0.2 2.125 5.16 10.39 37.92 25 1.5 0.077 0.33 0.2 2.393 5.71 5.0637.79 26 1.5 1.235 0.33 0.2 1.235 5.71 5.06 37.79 27 1.5 1 0.348 0.811.842 4.52 5.16 49.62 28 0.2 1 0.33 0.2 2.47 8.03 7.12 12.51 Example 529 1.5 3.47 0.33 0.2 — 5.71 5.06 37.79 30 1.5 3.636 0.164 0.2 — 5.972.51 37.72 31 1.5 3.299 0.501 0.2 — 5.44 7.70 37.86 32 1.5 3.125 0.6750.2 — 5.16 10.39 37.92 33 1.5 3.13 0.34 0.4 — 5.20 5.27 42.66 34 1.52.842 0.348 0.81 — 4.52 5.16 49.62 35 0.2 3.47 0.33 0.2 — 8.03 7.1212.51 Example 6 36 1.5 3.67 0.33 — — 6.11 5.12 33.73 37 1.5 3.836 0.164— — 6.38 2.54 33.67 38 1.5 3.508 0.492 — — 5.85 7.65 33.79 39 1.5 3.3360.664 — — 5.58 10.34 33.86 Mean bond Melting point strength of solder(kgf/mm²) Main peeling Ra Rmax No. layer (° C.) (n = 10) mode* (μm) (μm)Example 4 21 192 2.5 inside SC D 0.049 0.644 22 193 2.6 inside SC D0.051 0.668 23 184 2.2 inside SC D 0.055 0.752 24 179 2.9 inside SC D0.053 0.733 25 188 2.3 inside SC D 0.056 0.691 26 191 2.1 inside SL0.058 0.722 27 191 2.3 inside SL 0.063 0.765 28 190 2.7 inside SC D0.055 0.685 Example 5 29 189 2.7 inside SC D 0.035 0.370 30 194 3.1inside SC D 0.041 0.499 31 188 2.6 inside SC D 0.047 0.428 32 180 3.2inside SC D 0.044 0.488 33 191 2.8 inside SC D 0.048 0.402 34 194 2.3inside SL 0.035 0.388 35 191 2.8 inside SC D 0.046 0.465 Example 6 36197 2.7 inside SC D 0.105 0.854 37 204 2.4 inside SC D 0.097 0.856 38193 3.1 inside SC D 0.104 0.915 39 188 2.9 inside SC D 0.103 0.992*inside SC D = inside semiconductor device inside SL = inside solderlayer

Example 5

A device bonded substrate (No. 29) was prepared in the same manner as inExample 1, except that the structure of the solder layer 540 was changedto that wherein on the first Ag layer 500 having a thickness of 1.5 μm,an In layer 541 having a thickness of 0.33 μm, a second Ag layer 542having a thickness of 0.2 μm and a first Au10—Sn layer 543 having athickness of 3.47 μm were laminated in this order, as shown in FIG. 5.Similarly, 10 device bonded substrates were prepared, and the surfaceroughness and the bond strength of the device bonded substrates weremeasured in the same manner as in Example 1. As a result, Ra was 0.035μm, Rmax was 0.370 μm, the mean bond strength was 2.7 kgf/mm², and themodes of peeling were mainly “inside semiconductor device”. Further,substrates for device bonding No. 30 to No. 35 of the invention wereprepared by changing each thickness of the In layer and the Au10—Snlayer as shown in Table 2, and then measurement of bond strength wascarried out in the same manner as above. The results are set forth inTable 2.

Example 6

A device bonded substrate (No. 36) was prepared in the same manner as inExample 1, except that the structure of the solder layer 550 was changedto that wherein on the first Ag layer 500 having a thickness of 1.5 μm,an In layer 551 having a thickness of 0.33 μm and a first Au10—Sn layer552 having a thickness of 3.67 μm were laminated in this order, as shownin FIG. 6. Similarly, 10 device bonded substrates were prepared, and thesurface roughness and the bond strength of the device bonded substrateswere measured in the same manner as in Example 1. As a result, Ra was0.105 μm, Rmax was 0.854 μm, the mean bond strength was 2.7 kgf/mm², andthe modes of peeling were mainly “inside semiconductor device”. Further,substrates for device bonding No. 37 to No. 39 of the invention wereprepared by changing each thickness of the In layer and the Au10—Snlayer as shown in Table 2, and then measurement of bond strength wascarried out in the same manner as above. The results are set forth inTable 2.

Example 7

A device bonded substrate (No. 40) was prepared in the same manner as inExample 1, except that the structure of the solder layer 560 was changedto that wherein on the first Ag layer 500 having a thickness of 1.5 μm,a Bi layer 561 having a thickness of 0.33 μm, a second Ag layer 562having a thickness of 0.2 μm and a first Sn layer 563 having a thicknessof 3.47 μm were laminated in this order, as shown in FIG. 7. Similarly,10 device bonded substrates were prepared, and the surface roughness andthe bond strength of the device bonded substrates were measured in thesame manner as in Example 1. As a result, Ra was 0.044 μm, Rmax was0.410 μm, the mean bond strength was 2.5 kgf/mm², and the modes ofpeeling were mainly “inside semiconductor device”. Further, substratesfor device bonding No. 41 to No. 43 of the invention were prepared bychanging each thickness of the Bi layer and the Sn layer as shown inTable 3, and then measurement of bond strength was carried out in thesame manner as above. The results are set forth in Table 3.

TABLE 3 Thickness of Thickness of Thickness of Bi layer second Ag firstAg layer (melting layer Composition of (surface- point- (surface- solderlayer Melting Mean bond soomthing lowering soomthing Thickness of(balance is Sn) point of strength metal layer) metal layer) metal layer)first Sn layer Bi Ag solder layer (kgf/mm²) Main peeling Ra Rmax No.(μm) (μm) (μm) (μm) (wt %) (wt %) (° C.) (n = 10) mode* (μm) (μm) Ex- 401.5 0.33 0.2 3.47 6.96 38.47 196 2.5 inside SC D 0.044 0.410 ample 7 410.2 0.33 0.2 3.27 10.32 13.42 193 2.8 inside SC D 0.039 0.521 42 0.20.164 0.2 3.436 5.20 13.60 199 2.9 inside SC D 0.048 0.433 43 0.2 0.5010.2 3.099 15.46 13.24 178 2.7 inside SC D 0.043 0.458 Thickness ofThickness of Thickness of In layer second Ag first Ag layer (meltinglayer Composition of (surface- point- (surface- solder layer MeltingMean bond soomthing lowering soomthing Thickness of (balance is Sn)point of strength metal layer) metal layer) metal layer) first Sn layerIn Ag solder layer (kgf/mm²) Main peeling Ra Rmax No. (μm) (μm) (μm)(μm) (wt %) (wt %) (° C.) (n = 10) mode* (μm) (μm) Ex- 44 1.5 0.33 0.23.47 5.25 39.18 207 3.1 inside SC D 0.046 0.512 ample 8 45 0.2 0.33 0.23.27 7.85 13.79 202 2.5 inside SC D 0.049 0.484 46 0.2 0.164 0.2 3.4363.90 13.79 211 2.3 inside SL 0.041 0.511 47 0.2 0.501 0.2 3.099 11.9313.80 185 2.1 inside SL 0.047 0.498 *inside SC D = inside semiconductordevice inside SL = inside solder layer

Example 8

A device bonded substrate (No. 44) was prepared in the same manner as inExample 1, except that the structure of the solder layer 570 was changedto that wherein on the first Ag layer 500 having a thickness of 1.5 μm,an In layer 571 having a thickness of 0.33 μm, a second Ag layer 572having a thickness of 0.2 μm and a first Sn layer 573 having a thicknessof 3.47 μm were laminated in this order, as shown in FIG. 8. Similarly,10 device bonded substrates were prepared, and the surface roughness andthe bond strength of the device bonded substrates were measured in thesame manner as in Example 1. As a result, Ra was 0.046 μm, Rmax was0.512 μm, the mean bond strength was 3.1 kgf/mm², and the modes ofpeeling were mainly “inside semiconductor device”. Further, substratesfor device bonding No. 44 to No. 47 of the invention were prepared bychanging each thickness of the In layer and the Sn layer as shown inTable 3, and then measurement of bond strength was carried out in thesame manner as above. The results are set forth in Table 3.

Comparative Example 1

A substrate for device bonding (No. 20) was prepared in the same manneras in Example 1, except that the structure of the solder layer 580 waschanged to that wherein on the first Ag layer 500 having a thickness of1.5 μm, a first Au10—Sn layer 581 having a thickness of 1.735 μm, a Bilayer 582 having a thickness of 0.33 μm and a second Au10—Sn layer 583having a thickness of 1.735 μm were laminated in this order, as shown inFIG. 9. Using the substrate for device bonding, a device bondedsubstrate was prepared under the same bonding temperature and bondingconditions as in Example 1. Similarly, 10 device bonded substrates wereprepared, and the surface roughness and the bond strength of the devicebonded substrates were measured in the same manner as in Example 1. As aresult, Ra was 0.120 μm, Rmax was 1.06 μm, the mean bond strength was0.7 kgf/mm², and the modes of peeling were all “between semiconductordevice and solder”.

Comparative Example 2

A substrate for device bonding was prepared in the same manner as inExample 1, except that the structure of the solder layer 590 was changedto that wherein on the first Ag layer 500 having a thickness of 1.5 μm,a first Au10—Sn layer 591 having a thickness of 1.156 μm, a Bi layer 592having a thickness of 0.33 μm, a second Au10—Sn layer 593 having athickness of 1.156 μm, a second Ag layer 594 having a thickness of 0.2μm and a third Au10—Sn layer 595 having a thickness of 1.156 μm werelaminated in this order, as shown in FIG. 10. Using the substrate fordevice bonding, a device bonded substrate was prepared under the samebonding temperature and bonding conditions as in Example 1. Similarly,10 device bonded substrates were prepared, and the surface roughness andthe bond strength of the device bonded substrates were measured in thesame manner as in Example 1. As a result, Ra was 0.119 μm, Rmax was0.972 μm, the mean bond strength was 0.8 kgf/mm², and the modes ofpeeling were all “between semiconductor device and solder”.

Comparative Example 3

A device bonded substrate was prepared in the same manner as in Example1, except that the first Ag layer was not formed and the structure ofthe solder layer 5A0 was changed to that wherein a Bi layer 5A1 having athickness of 0.33 μm and a first Au10—Sn layer 5A2 having a thickness of3.67 μm were laminated in this order from the solder flow-out preventingPt side, as shown in FIG. 11. Similarly, 10 device bonded substrateswere prepared, and the surface roughness and the bond strength of thedevice bonded substrates were measured in the same manner as inExample 1. As a result, Ra was 0.131 μm, Rmax was 1.272 μm, the meanbond strength was 0.4 kgf/mm², and the modes of peeling were all“between semiconductor device and solder”.

Reference Example 1

A substrate for device bonding was prepared in the same manner as inExample 1, except that the first Ag layer was not formed and, as thesolder layer, a Sn—Pb solder layer 600 shown in FIG. 12, i.e., a layerhaving a structure consisting of a first Pb layer 601 having a thicknessof 0.55 μm, a first Sn layer 602 having a thickness of 1.45 μm, a secondPb layer 603 having a thickness of 0.55 μm and a second Sn layer 604having a thickness of 1.45 μm laminated in this order from the solderflow-out preventing Pt side, was formed. Using the substrate for devicebonding, a device bonded substrate was prepared at the same bondingtemperature as in Example 1. Similarly, 10 device bonded substrates wereprepared, and the bond strength of the device bonded substrates wasmeasured in the same manner as in Example 1. As a result, the mean bondstrength was 3.4 kgf/mm², and the modes of peeling were mainly “insidesemiconductor device”.

In FIGS. 13 to 16, photographs of polished sections of the substratesfor device bonding prepared in Examples 1 to 3 and Comparative Example 1are shown, respectively, and in FIGS. 17 to 20, three-dimensional imagesof the solder layer surfaces of these substrates obtained in themeasurement of surface roughness are shown, respectively.

1. A substrate for device bonding, comprising an electrode layer and asolder layer formed on the electrode layer, wherein the solder layer isa Pb-free solder layer comprising: (1) a base metal layer comprising (i)Sn, (ii) Sn and Au, or (iii) In, (2) one or more melting point-loweringmetal layers each of which comprises at least one metal selected fromthe group consisting of Bi, In (only in the case where the base metal isSn, or Sn and Au), Zn, Au (only in the case where the base metal is In)and Sb, and (3) one or more surface-smoothing metal layers each of whichcomprises at least one metal selected from the group consisting of Ag,Ni, Fe, Al, Cu and Pt, and each of the melting point-lowering metallayers is adjacent to any one of the surface-smoothing metal layers. 2.A process for producing a device bonded substrate, comprising placing adevice having an electrode on the solder layer of the substrate fordevice bonding of claim 1 in such a manner that the electrode of thedevice is brought into contact with the solder layer and then bondingthe device by reflow soldering.
 3. A process for producing a substratefor device bonding, comprising a solder layer-forming step for forming aPb-free solder layer on an electrode layer of the substrate, saidPb-free solder layer comprising: (1) a base metal comprising (i) Sn,(ii) Sn and Au, or (iii) In, (2) at least one metal selected from thegroup consisting of Bi, In (only in the case where the base metal is Sn,or Sn and Au), Zn, Au (only in the case where the base metal is In) andSb, and (3) at least one metal selected from the group consisting of Ag,Ni, Fe, Al, Cu and Pt, said Pb-free solder layer having a thickness of 1to 15 μm and a surface roughness (Ra) of not more than 0.11 μm, whereinthe solder layer-forming step includes one or more steps for forming alayer comprising the base metal, one or more steps for forming a meltingpoint-lowering metal layer comprising at least one metal selected fromthe group consisting of Bi, In (only in the case where the base metal isSn, or Sn and Au), Zn, Au (only in the case where the base metal is In)and Sb, and one or more steps for forming a surface-smoothing metallayer comprising at least one metal selected from the group consistingof Ag, Ni, Fe, Al, Cu and Pt, and immediately before and/or immediatelyafter the step for forming the melting point-lowering metal layer, anyone of the steps for forming the surface-smoothing metal layer iscarried out.
 4. The process of claim 3, wherein each of the meltingpoint-lowering metal layers is adjacent to any one of thesurface-smoothing metal layers.
 5. A process for producing a substratefor device bonding, comprising a bonding layer-forming step for forminga bonding layer comprising a transition metal on an electrode layer anda solder layer-forming step for forming a Pb-free solder layer on thebonding layer, said Pb-free solder layer comprising: (1) a base metalcomprising (i) Sn, (ii) Sn and Au, or (iii) In, (2) at least one metalselected from the group consisting of Bi, In (only in the case where thebase metal is Sn, or Sn and Au), Zn, Au (only in the case where the basemetal is In) and Sb, and (3) at least one metal selected from the groupconsisting of Ag, Ni, Fe, Al, Cu and Pt, said Pb-free solder layerhaving a thickness of 1 to 15 μm and a surface roughness (Ra) of notmore than 0.11 μm, wherein the solder layer-forming step includes one ormore steps for forming a layer comprising the base metal, one or moresteps for forming a melting point-lowering metal layer comprising atleast one metal selected from the group consisting of Bi, In (only inthe case where the base metal is Sn, or Sn and Au), Zn, Au (only in thecase where the base metal is In) and Sb, and one or more steps forforming a surface-smoothing metal layer comprising at least one metalselected from the group consisting of Ag, Ni, Fe, Al, Cu and Pt, andimmediately before and/or immediately after the step for forming themelting point-lowering metal layer, any one of the steps for forming thesurface-smoothing metal layer is carried out.
 6. The process of claim 5,wherein each of the melting point-lowering metal layers is adjacent toany one of the surface-smoothing metal layers.